The present invention relates to a semiconductor device and a method of designing it, and in particular to a semiconductor device comprising a plurality of internal circuits formed on a semiconductor chip, and supplied with different power supply voltages, and a protection circuit for protecting the internal circuits from an electrostatic discharge (ESD), and a method of designing such a semiconductor device.
Examples of the internal circuits formed on the same semiconductor chip, and supplied with different power supply voltages include a regulator circuit, a digital logic circuit, and an analog circuit. The power supply voltage for such internal circuits is generally supplied from outside of the chip, via power supply pads on the chip, to the power supply lines for the internal circuits, and the power supply pads are generally disposed in the peripheral part of the chip.
It is desirable that a protection circuit is positioned between the power supply pads and the internal circuits such that the surge voltage applied to the power supply pads at the time of ESD occurrence reaches the protection circuit before it reaches the internal circuits. Where a plurality of internal circuits receiving different power supply voltages are provided, it is desirable that separate protection elements are provided for protection against an excessive voltage between each power supply line for each internal circuit and the associated ground line, for protection against an excessive voltage between the power supply lines for the different internal circuits, and for protection against an excessive voltage between the ground lines for the different internal circuits.
Where a plurality of different protection circuits are provided, it is not possible to place all the protection circuits between the power supply pads and the internal circuits, and the surge voltage applied to the power supply pads may reach the internal circuits before reaching the protection circuits, and it may not be possible to provide a sufficient protection for the internal circuits.
Japanese Patent Kokai Publication No. 2000-208718 shows an arrangement in which protection is made for circuits receiving power supply voltages different from each other, and protection elements are disposed in an area closest to the power supply systems. Specifically, part of the protection elements are provided in the central area.
However, in the device shown in Japanese Patent Kokai Publication No. 2000-208718, the protection elements positioned in the central area are not necessarily positioned between the power supply pads and the internal circuits, and it was not possible to securely protect the internal circuits from the ESD surge voltages.